Even though digital communications equipment has met with widespread acceptance in a variety of technologies, telephone companies have been slow to integrate digital signalling subsystems and communication schemes into their well established copper wire networks. One of the principal reasons for such hesitation is the fact that a significant part, if not all, of an established telephone network employs traditional analog signalling equipment. Still, because of ever increasing user demand, regional Bell operating companies (RBOC's) currently provide leased-line digital services to sophisticated customers, typically by means of a digital (D4) channel bank diagrammatically illustrated at 10 in FIG. 1, through which digital services are provided by the network to digital signalling equipment located at a customer's premises 20.
D4 channel bank 10 typically contains a line interface unit (LIU) 11 which interfaces T1 (1.544 Mb/s) carrier traffic at one end of a T1 digital communications link 14. A second end of T1 link 14 may be connected to another office containing an operational support system (OSS) 16 located remotely with respect to terminal 10. D4 channel bank 10 also includes an office channel unit data port (OCU-DP) 12, which is coupled to LIU 11 via an intra bank PCM communications link 15, and interfaces bipolar signals carried by a local loop (e.g. a four-wire metallic link) 21 to (via receive link portion 21R) and from (via transmit link portion 21T) a digital data service termination (DDST) 22 which may be used to terminate the metallic loop 21, together with a data service unit/channel service unit (CSU/DSU) 23 located at the customer's premises 20.
The LIU 11 and OCU-DP 12 of D4 channel bank 10 have respective transmit/receive buffers associated with the respective ports of that unit. These buffers are controlled by a resident microcontroller for interfacing DS1-formatted data traffic from the line (T1 link 14) side of the channel bank, retiming the traffic as a bipolar data stream for transmission as a data stream from the D4 channel bank 10 to the customer's DSU/CSU site 20, and reconverting bipolar signals, supplied from the customer site 20 to OCU data port 12, into DS1 data frames for transmission over T1 link 14.
As shown in FIG. 2, an OCU-DP 12 contains a transmitter section 31, to which DS0 data from the four wire metallic loop 21 is supplied from the customer site termination equipment, and a receiver section 33, from which DS0 data is coupled to four wire metallic loop 21 for delivery to the customer site termination equipment. D4 channel bank 10 also includes a receive unit 34 and transmit unit 35. Transmit unit 35 (shown in greater detail in FIG. 5, to be described) supplies transmission control TX-CNTL signals via a transmission control link 41 in the form of a set of transmit sequence control leads (TWD, TSP, TSQ) for controlling the format of the transmissions, and a transmit data clock TDCLK, via a transmit data clock link 43, to transmitter section 31 of each OCU-DP 12. In response to these signals, the OCU-DP 12 decodes its respective channel select strobe and transmits data onto a transmit data (TDATA) bus lead in a respective preassigned one of a plurality (e.g. 24) of time division multiplexed channel unit time slots of a multi-channel (e.g. 24 channel) unit digroup within the D4 channel bank 10.
According to AT&T defined communication standards, the channel select strobe occurs at an 8 KHz rate and the transmission of eight bits per strobe corresponds to one 64 Kb/s (DS0) channel for a DS1 line. Transmit unit 35 collects the 192 bits (8 bits from each of the (24) channel units) from transmission data bus 45, appends a framing bit, and outputs the resulting DS1-formatted PCM data stream onto TPCM link 51, and an associated transmit clock signal via TCLK link 53 to line interface unit 11. An additional TPAM link 42 is provided so as to accommodate the insertion of one or more analog channel unit's data on the TPCM link 51.
Specifically, where the channel unit is an analog unit, rather than a digital unit, TPAMlink 42 provides for the transmission of pulse amplitude modulated (PAM) samples of analog signals to transmit unit 35 for subsequent conversion to PCM data bytes and insertion into the appropriate channel unit time slot of TPCM link 51. In addition, a transmission multiplexer control link TNEN 44 is coupled to transmit unit 35. When an analog channel unit is plugged into the backplane it asserts ground on link 44, during its respective timeslot, so as to inform the transmit unit 35 that the channel unit is an analog channel unit. During the transmission time slot assigned for that (analog) channel the assertion of ground on TNEN link 44 causes the state of the transmit unit's data transmission multiplexer to be switched to the output of an analog-to-digital encoder, through which analog data is digitally encoded for insertion into the time slot associated with that analog channel unit.
`A` and `B` signalling bits are also coupled to transmit unit 35 from an analog channel unit for insertion into the LSB position of the data byte of frame six (`A` bit), and frame twelve (`B` bit) of the superframe. The line interface unit 11 may convert the superframe framing format provided by transmit unit 35 to DS1 extended superframe format. The line interface unit 11 then couples the formatted DS1 data onto the digital carrier for transmission over T1 link 14. Incoming T1 carrier signals from T1 link 14 are received by line interface unit 11, and extended superframe format is converted into superframe formatted signals, as necessary. Payload or signalling bits are not altered. The DS1 data is output to a receive PCM link 61 and coupled to receive unit 34 and receiver section 33 of OCU-DP 12. The DS1 clock is recovered by LIU 11 and the recovered clock RCLK is coupled over receive clock RCLK link 63 to each of receive unit 34 and receiver section 33 of OCU-DP 12. For an analog channel unit, an RPAM link 62 is coupled from receive unit 34 to the receive section 33 of channel unit 12.
Receive unit 34 synchronizes its timing with the DS1 framing pattern of the received signal and supplies channel unit control signals over link 65 to receiver section 33, so as to allow each OCU-DP to decode its channel select strobe for the received data and to extract its corresponding byte of data from the associated time slot of data link 61. This data strobe timing is illustrated diagrammatically in FIG. 3, which shows sequential information (I) bits (eight bits per channel i) being asserted onto receive data RNPCM link 61 coincident with falling edges of sequential RCLK signals, thereby allowing for a one-half bit time of set-up and one-half bit time of hold. In the receive direction, there is an additional analog signalling link 62, which is provided to allow analog channel units to deliver PAM samples of analog signals (converted from PCM bytes) to be coupled from receive unit 34 to the appropriate analog channel unit. Control link 65 contains a set of sequence control leads that are employed to control receive signalling format, including the contents of frames six and twelve of a superframe. The receiver section 33 of the channel unit recovers the appropriate `A` or `B` signalling bit during the appropriate frame when the channel select strobe is active.
In the D4 channel bank, all OCU-DPs (channel units) 12 share the transmit and receive data links 45 and 61, as diagrammatically illustrated in FIG. 4, so that each channel unit has physical access to every DS0 time slot in a digroup (two twenty-four channel unit digroups A and B being shown in FIG. 4). However, time slot allotment is time division multiplexed under control of control and clock signals supplied by the transmit unit 35 for the transmit direction and by the receive unit 34 for the receive direction.
Referring now to FIG. 5, the configuration of transmit unit 35 is diagrammatically illustrated as comprising a multiplexer 70, a first input 71 of which is coupled to an analog-digital data encoder 73, and a second input 72 of which is coupled to a digital data storage element 74. Analog-digital data encoder 73 has its input coupled to receive analog data asserted on the analog TPAM lead 42, and is operative to digitize an analog signal level asserted by an analog channel unit on TPAM lead 42 into a digital data word for transmission over TPCM link 51 to LIU 11 under the control of transmission sequence signals TWD, TSQ, TSP generated by a control logic generator 75 on link 41. Control logic generator 75 is coupled to receive a system clock signal on clock input lead 78, and additionally generates both the data sampling clock TDCLK on lead 43 and the transmit clock TCLK on lead 53. The data sampling clock TDCLK on lead 43 is coupled to both encoder 73 and storage element 74. The transmission multiplexer control link TNEN 44 is coupled to the select input of multiplexer 70.
As described above, when an analog channel unit is plugged into the backplane it asserts ground on TNEN link 44, during its timeslot, so as to inform the transmit unit 35, specifically multiplexer 70, that the channel unit is an analog channel unit. If the channel unit is a digital channel unit or no channel unit is plugged into a respective backplane slot, then the TNEN lead 44 is held high (+5V) by a pull-up resistor 76. During the transmission time slot assigned for that (analog) channel unit, the analog channel unit asserts ground on the TNEN link 44, which causes the state of the transmit unit's data transmission multiplexer 70 to be switched to the output of encoder 73, through which analog data is digitally encoded for insertion into the time slot associated with that analog channel unit. On the other hand, as noted above, if the channel unit is not an analog channel unit, ground is not asserted on the TNEN lead 44, so that multiplexer 70 couples storage element 74 to the TPCM lead 51.
Similar to the TNEN lead 44, the TDATA lead 45 is coupled to a pull-up resistor 77 for pulling the TDATA lead high (+5V), in the absence of the assertion of a low data value on the TDATA lead 45 by a digital channel unit, a block diagram of which is shown in FIG. 6. Within the digital channel unit, TXDATA data to be transmitted, sourced from a data source 81, is clocked into a storage buffer 82 by the 8 KHz channel select strobe. Each byte of data is then loaded into and shifted out of a shift buffer 83 under the control of a DS1TX control signal generator 84, in accordance with the transmission sequence signals TWD, TSQ, TSP supplied by control logic generator 75 on link 41, and TDCLK signals on line 43. In the transmit unit 35, shown in FIG. 5, the successive data bit representative voltage levels asserted by a digital channel unit on the TDATA link 45 are sampled and stored in storage element 74, on the negative-going clock edge of the TDCLK signal on line 43. The data is then clocked out on TPCM link 51 to the LIU 11 together with a clock signal on TCLK lead 53. FIG. 7 is a timing diagram showing relationships between TDATA and TDCLK signals, and between TPCM and TCLK signals.
Where an available backplane channel unit slot is unoccupied, namely, no channel unit (either analog or digital) is plugged into that slot, the TDATA lead 45 is held high at +5V (or continuously at a logical `1`) by pull-up resistor 77. This continuously asserted high on the TDATA lead 45 is repeatedly sampled by the falling edge of the TDCLK lead 43 input to storage element 74 as a data value of `1`, during the unoccupied channel unit's time slot, so that a continuous sequence of `1`s may be transmitted over TPCM link 51 during the unoccupied time slot, thereby maintaining a high `1`s density and preventing the generation of a false yellow alarm code.
Because the value of pull-up resistor 77 is low (e.g. on the order of 100-400 Kohms) and is typically part of an input gate of a CMOS or TTL chip, the effective charging time of TDATA lead 45, governed by the time constant product of the pull-up resistor 77 and the inherent capacitance of the TDATA lead 45, is longer (e.g. on the order of one microsecond) than several bit times of a TDATA byte. As a consequence, where there is an unoccupied channel unit time slot immediately following the transmission time slot of an occupied channel unit, there is the potential for the zero bit value of the last data bit of the occupied channel time slot `bleeding over` into and thereby corrupting an initial one or two bit portion of the above-described all `1`s sequence to be transmitted during the unoccupied channel time slot.
More particularly, as explained above, an unoccupied channel unit time slot should cause the state of the TDATA lead 45 to be held continuously unmodulated at the high (pulled-up +5 v) value for the duration of the unoccupied channel's time slot. However, if the last bit of the occupied channel time slot is low (e.g. 0 volts), the relatively long charging time required to pull the TDATA lead 45 up to +5V will extend into or overlap with the first and possibly second bit times of the unoccupied time slot. As a result, during such bit times, the voltage level on TDATA lead 45 may not yet have reached the threshold value corresponding to a logical `1`. In this case, up to the first two bits of the intended data string of all `1`s that would otherwise be forwarded over the TPCM lead 51 to the LIU 11 will be sampled as logical `0`s rather than logical `1`s, thereby corrupting the all `1`s sequence of the unoccupied channel time slot. Such a condition causes problems in downstream multijunction circuits, since in a multijunction circuit topology, multiple branches are logically ANDed, so that the occurrence of one or more zero's in place of `1`s in the data stream will create errors in the multi junction unit control link.